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utron ut62l64c rev . 1.3 8k x 8 bit low power cmos sram ? revision history r e v i s i o n d e s c r i p t i o n r e l e a s e d d a t e rev. 0.1 original may 3,2001 rev. 1.0 release feb.26,2002 rev. 1.1 revised - improve i dr from 20 a to 10 a (ll-version , max.) may 14,2002 rev. 1.2 1. revised single power supply : 3.3v 3.0v~3.6v 2. add extended temperature : -20 j ~85 j 3. revised ?order information? : add extended parts 4. ac/dc characteristics : -add extended temperature -icc1 (typ):12 6ma, ic c 1 (max) : 20 10ma -icc2 (typ):6 12ma, ic c 2 (max) : 10 20ma jul 30,2002 rev. 1.3 add order information for lead free product may 15,2003 utron technology inc. p80060 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiw an, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 1
utron ut62l64c rev . 1.3 8k x 8 bit low power cmos sram ? features access time : 35/70ns (max.) low power consumption: operating : 30/20 ma (typical) standby : 1.5ma (typical) normal 1 a (typical) l-version 0.5 a (typical) ll-version single 3.0v~3.6v power supply operating temperature : commerical : 0 j ~70 j extended : -20 j ~85 j all inputs and outputs ttl compatible fully static operation three state outputs data retention voltage : 1.5v (min.) package : 28-pin 600mil pdip 28-pin 330 mil sop substrate connected : vcc functional block diagram deco der i/o d a t a ci rc ui t co ntrol ci rc ui t 8k ?? 8 me mo ry array c o l u m n i/o oe we a0- a 12 vcc vss i/o 1 - i/o 8 ce ce2 general description the ut62l64c is a 65,536-bits low power cmos static random access memory organized as 8,192 words by 8 bits. it is fabricated using high performance, high reliability cmos technology. easy memory expansion is provided by using two chip enable input.( ce ,ce2) the ut62l64c operates from a single 3.3v power supply and all inputs and outputs are fully ttl compatible. pin configuration a12 a7 a6 a5 a4 a3 a2 a1 a0 i/ o 1 i/ o 2 vc c a8 a9 a11 a10 i/ o 8 i/ o 7 i/ o 6 i/ o 5 i/ o 4 i/ o 3 vs s ut62l64c so p/pdip 28 14 13 12 11 10 9 8 7 6 5 4 3 2 1 17 16 15 20 19 18 22 23 24 25 26 27 21 we oe ce 2 nc ce p ad description s y m b o l d e s c r i p t i o n a0 - a12 address inputs i/o1 - i/o8 data inputs/outputs ce ,ce2 chip enable inputs we write enable input oe output enable input v cc p o w e r s u p p l y v ss g r o u n d n c utron technology inc. p80060 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiw an, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 2
utron ut62l64c rev . 1.3 8k x 8 bit low power cmos sram ? absolute maximum ratings * p a r a m e t e r s y m b o l r a t i n g u n i t terminal voltage with respect to v ss v term -0.5 to 4.5 v c o m m e r i c a l t a 0 to 70 j operating temperature e x t e n d e d t a -20 to 85 j storage temperature t stg -65 to 150 j power dissipation p d 1 w dc output current i out 5 0 m a soldering temperature (under 10 sec) tsolder 260 j *stresses greater than those listed under ?absolute maximum ra tings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device or any other conditions abov e those indicated in the operational sections of this specification is not implied. exposure to the absolute maximum rating conditions for extended period may affec t device r e liability . truth table mode ce ce2 oe we i/o operation supply current standby h x x x high - z i sb, i sb1 s t a n d b y x l x x h i g h - z i sb, i sb1 output disable l h h h high - z i cc, i cc1, i cc2 r e a d l h l h d out i cc, i cc1, i cc2 w r i t e l h x l d in i cc, i cc1, i cc2 note: h = v ih , l=v il , x = don't care. dc electrical characteristics (v cc = 3.0~3.6v, t a = 0 j to 70 j / -20 j to 85 j (e)) pa ra m e t e r s y m b o l test condit i o n m i n . t y p . ma x . u n i t input high voltage v ih ? 1 2 . 2 - vcc+ 0 . 5 v input low voltage v il ? 2 - 0 . 5 - 0 . 6 v input leakage current i li v ss ?? v in ?? v cc - 1 - 1 a output leakage current i lo v ss ?? v i/o ?? v cc ce = v ih or ce2= v il or oe = v ih or we = v il - 1 - 1 a output high voltage v oh i oh = - 1ma 2.4 - - v output low voltage v ol i ol = 4ma - - 0.4 v - 35 - 30 40 ma i cc cy cle time=min,i i/o = 0 m a ce = v il , ce2= v ih - 70 - 20 30 ma icc1 ce =0.2v; i i/o = 0ma other pins at 0.2v or vcc-0.2v; tc y c l e = 1us - 6 1 0 m a operating pow e r supply current icc2 ce =0.2v; i i/o = 0 m a other pins at 0.2v or vcc-0.2v tc y c l e = 500ns - 1 2 2 0 m a n o r m a l - 1 1 0 m a standby current (t t l ) i sb ce = v ih or ce2= v il other pins= v il or v ih - l/- ll - 0.3 3 ma n o r m a l - 1 . 5 5 m a - l 1 100 a standby current (cmos) i sb 1 ce ? v cc -0.2v or ce2 ?? 0.2v , other pins at 0.2v or vcc-0.2v - ll - 0.5 50 a notes: 1. overshoot : vcc+3.0v fo r pulse width less than 10ns. 2. undershoot : vss-3.0v fo r pulse width less than 10ns. 3. overshoot and undershoot ar e sampled, not 100% tested. utron technology inc. p80060 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiw an, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 3
utron ut62l64c rev . 1.3 8k x 8 bit low power cmos sram ? c a p a c i t a n c e (t a =25 j , f=1.0mhz) p a r a m e t e r s y m b o l m i n . m a x u n i t input capacitance c in - 8 p f input/output capacitance c i/o - 1 0 p f note : these parameters are guaranteed by device characterization, but not production tested. a c t e s t c o n d i t i o n s input pulse levels 0v to 3.0v input rise and fall times 5ns input and output timing reference levels 1.5v output load c l = 100pf, i oh /i ol = -1ma/4 ma ac electrical characteristics (v cc = 3.0~3.6v, t a = 0 j to 70 j / -20 j to 85 j (e)) (1) read cycle u t 6 2 l 6 4 c - 3 5 u t 6 2 l 6 4 c - 7 0 parameter symbol m i n . m a x . m i n . m a x . unit read cycle time t rc 3 5 - 7 0 - n s a ddress a ccess time t aa - 3 5 - 7 0 n s chip enable access time t ace - 3 5 - 7 0 n s output enable access time t oe - 2 5 - 3 5 n s chip enable to output in low-z t clz* 1 0 - 1 0 - n s output enable to output in low-z t olz* 5 - 5 - n s chip disable to output in high-z t chz* - 2 5 - 3 5 n s output disable to output in high-z t ohz* - 2 5 - 3 5 n s output hold from address change t oh 5 - 5 - n s (2) write cycle u t 6 2 l 6 4 c - 3 5 u t 6 2 l 6 4 c - 7 0 p a r a m e t e r s y m b o l m i n . m a x . m i n . m a x . unit write cy cle time t wc 3 5 - 7 0 - n s address valid to end of write t aw 3 0 - 6 0 - n s chip enable to end of write t cw 3 0 - 6 0 - n s address set-up time t as 0 - 0 - n s write pulse width t wp 2 5 - 5 0 - n s write recov e ry time t wr 0 - 0 - n s data to write time overlap t dw 2 0 - 3 0 - n s data hold from end of write-time t dh 0 - 0 - n s output ac tive from end of write t ow * 5 - 5 - n s write to output in high-z t wh z * - 1 5 - 2 5 n s *these parameters are guaranteed by device char acterization, but not production tested. utron technology inc. p80060 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiw an, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 4
utron ut62l64c rev . 1.3 8k x 8 bit low power cmos sram ? timing waveforms read cycle 1 (address controlled) (1,2) t rc t aa d a ta v a l i d a d dres s do ut t oh t oh pr evi ous dat a v a li d read cycle 2 ( ce and ce2 and oe controlled) (1,3,4,5) t rc t aa t ac e t oe t oh z t cl z t oh t ol z h i gh- z d a ta v a l i d h i gh- z t ch z a d dr ess ce2 do u t ce oe notes : 1. we is high for read cy cle. 2.device is continuously selected oe =low , ce =low , ce2=high . 3.address must be valid prior to or coincident w i th ce =low , ce2=high; otherw i se t aa is the limiting parameter. 4.t clz , t ol z , t chz and t ohz are specified w i th c l =5pf. transition is measured ? 500mv from steady state. 5.at any given temperature and voltage condition, t chz is less than t clz,, t ohz is less than t ol z . utron technology inc. p80060 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiw an, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 5
utron ut62l64c rev . 1.3 8k x 8 bit low power cmos sram ? write cycle 1 ( we controlled) (1,2,3,5,6) t wc t aw t cw t as t wp t wh z t ow t wr hi g h - z (4 ) ( 4 ) a ddr es s ce2 ce we d out di n d a t a v a lid t dw t dh write cycle 2 ( ce and ce2 controlled) (1,2,5,6) t wc t aw t cw t as t wr t wp t wh z t dw t dh d a t a v a lid h i gh- z (4 ) a ddr es s ce2 ce we d out di n utron technology inc. p80060 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiw an, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 6
utron ut62l64c rev . 1.3 8k x 8 bit low power cmos sram ? notes : 1. we , ce must be high or ce2 must be low during all address transitions. 2.a w r ite occurs during the overlap of a low ce , high ce2, low we . 3.during a we controlled w r ite cy cle w i th oe low , t wp must be greater than t wh z +t dw to allow the drivers to turn off and data to be placed on the bus. 4.during this period, i/o pins are in the out put state, and input signals must not be applied. 5.if the ce low transition and ce2 high transition o ccurs simultaneously w i th or after we low transition, the outputs remain in a high impedance state. 6.t ow and t wh z are specified w i th c l = 5pf. transition is measured ? 500mv from steady state. data retention characteristics (t a = 0 j to 70 j / -20 j to 85 j (e)) p a r a m e t e r s y m b o l test c o n d i t i o n m i n . t y p . m a x . u n i t vc c for data retention v dr ce ? v cc -0.2v or ce2 d 0.2v 1 . 5 - 3 . 6 v -l - 1 5 0 p a data retention current i dr vcc=2.5v ce ? v cc -0.2v or ce2 d 0.2v -ll - 0 . 5 1 0 p a chip dis able to data retention time t cdr see data retention waveforms (below) 0 - - n s recov e ry time t r t rc* - - n s t rc* = read cy cle time data retention waveform low vcc data retention wav e form (1) ( ce controlled) v dr ? 1. 5v ce ? v cc -0 .2 v v cc ( m i n . ) v cc ( m i n . ) v ih v ih v cc t r t cd r ce low vcc data retention wav e form (2) (ce2 controlled) v dr ? 1. 5v v cc ( m i n . ) v cc t r t cd r ce2 ?? 0. 2 v v il ce2 v cc ( m i n . ) v il utron technology inc. p80060 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiw an, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 7
utron ut62l64c rev . 1.3 8k x 8 bit low power cmos sram ? package outline dimension 28 pin 600 mil pdip package outline dimension unit sy mbol i n c h ( b a s e ) m m ( r e f ) a 1 0 . 0 1 0 ( m i n ) 0 . 2 5 4 ( m i n ) a2 0.150 ? 0 . 0 0 1 3 . 8 1 0 ? 0.254 b 0.018 ? 0 . 0 0 5 0 . 4 5 7 ? 0.127 c 0.010 ? 0 . 0 0 4 0 . 2 5 4 ? 0.102 d 1.460 ? 0 . 0 0 5 3 7 . 0 8 4 ? 0.127 e 0.600 ? 0 . 0 1 0 1 5 . 2 4 0 ? 0.254 e 0 . 1 0 0 ( t y p ) 2 . 5 4 0 ( t y p ) eb 0.640 ? 0 . 0 3 1 6 . 2 5 6 ? 0.762 l 0.130 ? 0 . 0 1 0 3 . 3 0 2 ? 0.254 c 0 o ~15 o 0 o ~15 o utron technology inc. p80060 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiw an, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 8
utron ut62l64c rev . 1.3 8k x 8 bit low power cmos sram ? 28 pin 330 mil sop package outline dimension unit sy mbol i n c h ( b a s e ) m m ( r e f ) a 0.112 (max) 2.845 (max) a 1 0 . 0 0 4 ( m i n ) 0 . 1 0 2 ( m i n ) a2 0.098 ? 0 . 0 0 5 2 . 4 8 9 ? 0.127 b 0 . 0 1 6 ( t y p ) 0 . 4 0 6 ( t y p ) c 0 . 0 1 0 ( t y p ) 0 . 2 5 4 ( t y p ) d 0.713 ? 0 . 0 0 5 1 8 . 1 1 0 ? 0.127 e 0.331 ? 0 . 0 0 5 8 . 4 0 7 ? 0.127 e1 0.465 ? 0 . 0 1 2 1 1 . 8 1 1 ? 0.305 e 0 . 0 5 0 ( t y p ) 1 . 2 7 0 ( t y p ) l 0.0404 ? 0 . 0 0 8 1 . 0 2 5 5 ? 0.203 l1 0.067 ? 0 . 0 0 8 1 . 7 0 2 ? 0.203 s 0.047 (max) 1.194 (max) y 0 . 0 0 3 ( m a x ) 0 . 0 7 6 ( m a x ) c 0 o ?? 10 o 0 o ?? 10 o utron technology inc. p80060 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiw an, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 9
utron ut62l64c rev . 1.3 8k x 8 bit low power cmos sram ? ordering information commerical temperature part no. access time(ns) standby current ( p a) (typ.) package ut62l64cpc-35 35 1.5ma 28 pin pdip u t 6 2 l 6 4 c p c - 3 5 l 3 5 1 a 28 pin pdip u t 6 2 l 6 4 c p c - 3 5 l l 3 5 0.5 a 28 pin pdip ut62l64cpc-70 70 1.5ma 28 pin pdip u t 6 2 l 6 4 c p c - 7 0 l 7 0 1 a 28 pin pdip u t 6 2 l 6 4 c p c - 7 0 l l 7 0 0.5 a 28 pin pdip ut62l64csc-35 35 1.5ma 28 pin sop u t 6 2 l 6 4 c s c - 3 5 l 3 5 1 a 28 pin sop u t 6 2 l 6 4 c s c - 3 5 l l 3 5 0.5 a 28 pin sop ut62l64csc-70 70 1.5ma 28 pin sop u t 6 2 l 6 4 c s c - 7 0 l 7 0 1 a 28 pin sop u t 6 2 l 6 4 c s c - 7 0 l l 7 0 0.5 a 28 pin sop extended temperature part no. access time(ns) standby current ( p a) (typ.) package ut62l64cpc-35e 35 1.5ma 28 pin pdip u t 6 2 l 6 4 c p c - 3 5 l e 3 5 1 a 28 pin pdip u t 6 2 l 6 4 c p c - 3 5 l l e 3 5 0.5 a 28 pin pdip ut62l64cpc-70e 70 1.5ma 28 pin pdip u t 6 2 l 6 4 c p c - 7 0 l e 7 0 1 a 28 pin pdip u t 6 2 l 6 4 c p c - 7 0 l l e 7 0 0.5 a 28 pin pdip ut62l64csc-35e 35 1.5ma 28 pin sop u t 6 2 l 6 4 c s c - 3 5 l e 3 5 1 a 28 pin sop u t 6 2 l 6 4 c s c - 3 5 l l e 3 5 0.5 a 28 pin sop ut62l64csc-70e 70 1.5ma 28 pin sop u t 6 2 l 6 4 c s c - 7 0 l e 7 0 1 a 28 pin sop u t 6 2 l 6 4 c s c - 7 0 l l e 7 0 0.5 a 28 pin sop utron technology inc. p80060 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiw an, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 10
utron ut62l64c rev . 1.3 8k x 8 bit low power cmos sram ? ordering information (for lead free product) commerical temperature part no. access time(ns) standby current ( p a) (typ.) package ut62l64cpcl-35 35 1.5ma 28 pin pdip u t 6 2 l 6 4 c p c l - 3 5 l 3 5 1 a 28 pin pdip u t 6 2 l 6 4 c p c l - 3 5 l l 3 5 0.5 a 28 pin pdip ut62l64cpcl-70 70 1.5ma 28 pin pdip u t 6 2 l 6 4 c p c l - 7 0 l 7 0 1 a 28 pin pdip u t 6 2 l 6 4 c p c l - 7 0 l l 7 0 0.5 a 28 pin pdip ut62l64cscl-35 35 1.5ma 28 pin sop u t 6 2 l 6 4 c s c l - 3 5 l 3 5 1 a 28 pin sop u t 6 2 l 6 4 c s c l - 3 5 l l 3 5 0.5 a 28 pin sop ut62l64cscl-70 70 1.5ma 28 pin sop u t 6 2 l 6 4 c s c l - 7 0 l 7 0 1 a 28 pin sop u t 6 2 l 6 4 c s c l - 7 0 l l 7 0 0.5 a 28 pin sop extended temperature part no. access time(ns) standby current ( p a) (typ.) package ut62l64cpcl-35e 35 1.5ma 28 pin pdip u t 6 2 l 6 4 c p c l - 3 5 l e 3 5 1 a 28 pin pdip u t 6 2 l 6 4 c p c l - 3 5 l l e 3 5 0.5 a 28 pin pdip ut62l64cpcl-70e 70 1.5ma 28 pin pdip u t 6 2 l 6 4 c p c l - 7 0 l e 7 0 1 a 28 pin pdip u t 6 2 l 6 4 c p c l - 7 0 l l e 7 0 0.5 a 28 pin pdip ut62l64cscl-35e 35 1.5ma 28 pin sop u t 6 2 l 6 4 c s c l - 3 5 l e 3 5 1 a 28 pin sop u t 6 2 l 6 4 c s c l - 3 5 l l e 3 5 0.5 a 28 pin sop ut62l64cscl-70e 70 1.5ma 28 pin sop u t 6 2 l 6 4 c s c l - 7 0 l e 7 0 1 a 28 pin sop u t 6 2 l 6 4 c s c l - 7 0 l l e 7 0 0.5 a 28 pin sop utron technology inc. p80060 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiw an, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 11
utron ut62l64c rev . 1.3 8k x 8 bit low power cmos sram ? this page is left blank intentionally. utron technology inc. p80060 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiw an, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 12

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